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» PPM Reduction on Embedded Memories in System on Chip
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2011
12 years 11 months ago
Exploiting Half-Wits: Smarter Storage for Low-Power Devices
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower than recommended by a microcontroller’s specifications to reduce energy consum...
Mastooreh Salajegheh, Yue Wang, Kevin Fu, Anxiao J...
MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
14 years 24 days ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...
WWIC
2005
Springer
197views Communications» more  WWIC 2005»
14 years 1 months ago
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications
The needs for run-time data storage in modern wired and wireless network applications are increasing. Additionally, the nature of these applications is very dynamic, resulting in ...
Stylianos Mamagkakis, Christos Baloukas, David Ati...
CASES
2007
ACM
13 years 11 months ago
Stack size reduction of recursive programs
For memory constrained environments like embedded systems, optimization for program size is often as important, if not more important, as optimization for execution speed. Commonl...
Stefan Schäckeler, Weijia Shang
NOCS
2007
IEEE
14 years 1 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...