230 search results - page 29 / 46 » PPM Reduction on Embedded Memories in System on Chip |
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
CHES
2007
Springer
14 years 1 months ago
2007
Springer
Replay attacks are often the most costly attacks to thwart when dealing with off-chip memory integrity. With a trusted System-on-Chip, the existing countermeasures against replay r...
RTAS
1997
IEEE
13 years 11 months ago
1997
IEEE
3rd IEEE Real-time Technology and Applications Symposium (RTAS), June 1997 in Montreal, Canada Cache-partitioning techniques have been invented to make modern processors with an e...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper explores the use of dynamic compilation for continuing execution even if one or more of the memory banks used by an application become temporarily unavailable (but th...
TPDS
2010
13 years 5 months ago
2010
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...