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» PPM Reduction on Embedded Memories in System on Chip
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HOTI
2008
IEEE
14 years 1 months ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
CODES
2007
IEEE
14 years 1 months ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
CASES
2006
ACM
14 years 1 months ago
Memory optimization by counting points in integer transformations of parametric polytopes
Memory size reduction and memory accesses optimization are crucial issues for embedded systems. In the context of affine programs, these two challenges are classically tackled by ...
Rachid Seghir, Vincent Loechner
AHS
2006
IEEE
119views Hardware» more  AHS 2006»
14 years 1 months ago
Particle Swarm Optimization with Discrete Recombination: An Online Optimizer for Evolvable Hardware
Self-reconfigurable adaptive systems have the possibility of adapting their own hardware configuration. This feature provides enhanced performance and flexibility, reflected i...
Jorge Peña, Andres Upegui, Eduardo Sanchez
RTAS
2010
IEEE
13 years 5 months ago
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...
Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele