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» PPM Reduction on Embedded Memories in System on Chip
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TC
2008
13 years 7 months ago
Secure Memory Accesses on Networks-on-Chip
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Ch...
Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic...
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
14 years 22 days ago
Reconfigurable Fast Memory Management System Design for Application Specific Processors
This paper presents the design and implementation of the new Active Memory Manager Unit (AMMU) designed to be embedded into System-on-Chip CPUs. The unit is implemented using VHDL...
S. Kagan Agun, J. Morris Chang
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
13 years 11 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
RTCSA
2005
IEEE
14 years 1 months ago
An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems
Garbage collection considerably increases programmer productivity and software quality. However, it is difficult to implement garbage collection both efficiently and suitably fo...
Matthias Meyer
ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
13 years 12 months ago
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
George S. Taylor, Simon W. Moore, Steve Wilcox, Pe...