Sciweavers

114 search results - page 12 / 23
» PVS: A Prototype Verification System
Sort
View
DAC
2005
ACM
13 years 9 months ago
Matlab as a development environment for FPGA design
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
Tejas M. Bhatt, Dennis McCain
ETFA
2006
IEEE
13 years 11 months ago
Verification of The Minimum Cost Forwarding Protocol for Wireless Sensor Networks
Wireless sensor networks (WSN) consist of small self-contained devices with computational, sensing and wireless communication capabilities. They allow flexible, powerful, tetherles...
William D. Henderson, Steven Tron
DIM
2008
ACM
13 years 9 months ago
Minimal information disclosure with efficiently verifiable credentials
Public-key based certificates provide a standard way to prove one's identity, as attested by some certificate authority (CA). However, plain certificates provide a binary ide...
David Bauer, Douglas M. Blough, David Cash
FDL
2007
IEEE
14 years 1 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
ETS
2010
IEEE
140views Hardware» more  ETS 2010»
13 years 8 months ago
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy
This paper explores the concept of design diversity redundancy applied to mixed-signal (MS) circuit blocks, as a proposal to increase system reliability. Three different implement...
Gabriel de M. Borges, Luiz F. Gonçalves, Ti...