214 search results - page 27 / 43 » Packet Reordering in Network Processors |
112
Voted
MICRO
2009
IEEE
15 years 9 months ago
2009
IEEE
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
99
Voted
SPLST
2003
15 years 4 months ago
2003
Abstract. In this paper we present an all-optical network architecture and a systolic routing protocol for it. The sparse optical torus network consists of an n×n torus, where pro...
156
Voted
ERSA
2010
15 years 19 days ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
150
Voted
TON
2010
14 years 9 months ago
2010
This paper presents Interleaved Stratified Timer Wheels as a novel priority queue data structure for traffic shaping and scheduling in packet-switched networks. The data structure ...
96
Voted
TC
2008
15 years 2 months ago
2008
Component failures and planned component replacements cause changes in the topology and routing paths supplied by the interconnection network of a parallel processor system over ti...