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» Packet Routing in Dynamically Changing Networks on Chip
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FPGA
2001
ACM
162views FPGA» more  FPGA 2001»
14 years 1 months ago
Reprogrammable network packet processing on the field programmable port extender (FPX)
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...
John W. Lockwood, Naji Naufel, Jonathan S. Turner,...
ICC
1997
IEEE
14 years 29 days ago
Removing Instability and Maximizing Throughput in a Multicast Shuffle-Exchange Network
Multicast capability can be incorporated into any interconnection networks by using a general packet replication scheme previously proposed in [4]. The network can then be used fo...
Cathy W. Chan, Soung C. Liew
SPAA
1994
ACM
14 years 25 days ago
Bounds on the Greedy Routing Algorithm for Array Networks
We analyze the performance of greedy routing for array networks by providing bounds on the average delay and the average number of packets in the system for the dynamic routing pr...
Michael Mitzenmacher
ISCA
2009
IEEE
214views Hardware» more  ISCA 2009»
14 years 3 months ago
Phastlane: a rapid transit optical routing network
Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable c...
Mark J. Cianchetti, Joseph C. Kerekes, David H. Al...
SIGCOMM
2000
ACM
14 years 1 months ago
FIRE: Flexible intra-AS routing environment
Current routing protocols are monolithic, specifying the algorithm used to construct forwarding tables, the metric used by the algorithm (generally some form of hop-count), and th...
Craig Partridge, Alex C. Snoeren, W. Timothy Stray...