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GLVLSI
2006
IEEE
115views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
Song Peng, Rajit Manohar
ICCAD
2009
IEEE
113views Hardware» more  ICCAD 2009»
13 years 5 months ago
A performance analytical model for Network-on-Chip with constant service time routers
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
Nikita Nikitin, Jordi Cortadella
CISS
2008
IEEE
14 years 1 months ago
A linear integer programming approach to analyze P2P media streaming
Recent advancement in peer-to-peer (P2P) technologies has enabled a wide range of new applications. In this paper, we present mixed integer programming (MIP) formulations to analy...
Fulu Li, Jianwei Huang, Andrew Lippman
INFOCOM
2010
IEEE
13 years 5 months ago
Cooperative Resource Management in Cognitive WiMAX with Femto Cells
Abstract—WiMAX with femto cells is a cost-effective nextgeneration broadband wireless communication system. Cognitive Radio (CR) has recently emerged as a promising technology to...
Jin Jin, Baochun Li
MEMOCODE
2007
IEEE
14 years 1 months ago
Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
Cheng-Hong Li, Rebecca L. Collins, Sampada Sonalka...