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FCCM
2006
IEEE
120views VLSI» more  FCCM 2006»
14 years 1 months ago
FPGAs, GPUs and the PS2 - A Single Programming Methodology
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
APVIS
2007
13 years 9 months ago
Adaptive sampling in three dimensions for volume rendering on GPUs
Direct volume rendering of large volumetric data sets on programmable graphics hardware is often limited by the amount of available graphics memory and the bandwidth from main mem...
Martin Kraus, Magnus Strengert, Thomas Klein, Thom...
DGCI
2005
Springer
14 years 1 months ago
Increasing Interconnection Network Connectivity for Reducing Operator Complexity in Asynchronous Vision Systems
Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients ...
Valentin Gies, Thierry M. Bernard
VIS
2004
IEEE
134views Visualization» more  VIS 2004»
14 years 8 months ago
Projecting Tetrahedra without Rendering Artifacts
Hardware-accelerated direct volume rendering of unstructured volumetric meshes is often based on tetrahedral cell projection, in particular, the Projected Tetrahedra (PT) algorith...
David S. Ebert, Martin Kraus, Wei Qiao
PC
2007
343views Management» more  PC 2007»
13 years 7 months ago
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexa...