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» Parallel Global Routing Algorithms for Standard Cells
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CEC
2009
IEEE
14 years 4 days ago
Parallel global optimisation meta-heuristics using an asynchronous island-model
Abstract— We propose an asynchronous island-model algorithm distribution framework and test the popular Differential Evolution algorithm performance when a few processors are ava...
Dario Izzo, Marek Rucinski, Christos Ampatzis
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
14 years 1 months ago
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Paul Zuber, Armin Windschiegl, Raúl Medina ...
ASAP
2007
IEEE
95views Hardware» more  ASAP 2007»
14 years 1 months ago
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multicore architect...
Sumit D. Mediratta, Jeffrey T. Draper
ESCIENCE
2007
IEEE
13 years 11 months ago
Grid-Enabling an Efficient Algorithm for Demanding Global Optimization Problems in Genetic Analysis
Abstract. We study the implementation on grid systems of an efficient algorithm for demanding global optimization problems. Specifically, we consider problems arising in the geneti...
Mahen Jayawardena, Sverker Holmgren
ASAP
2005
IEEE
135views Hardware» more  ASAP 2005»
14 years 1 months ago
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in w...
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu...