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ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
15 years 8 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
IEEEPACT
2005
IEEE
15 years 8 months ago
Performance Analysis of System Overheads in TCP/IP Workloads
Current high-performance computer systems are unable to saturate the latest available high-bandwidth networks such as 10 Gigabit Ethernet. A key obstacle in achieving 10 gigabits ...
Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Rona...
LCN
2003
IEEE
15 years 7 months ago
An Optoelectronic Multi-Terabit CMOS Switch Core for Local Area Networks
Optoelectronic integrated circuits can support thousands of integrated optical laser diodes and photodetectors bonded to a high-performance CMOS substrate, and can be used in the ...
Honglin Wu, Amir Gourgy, Ted H. Szymanski
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ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 6 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
CPAIOR
2006
Springer
15 years 6 months ago
An Efficient Hybrid Strategy for Temporal Planning
Temporal planning (TP) is notoriously difficult because it requires to solve a propositional STRIPS planning problem with temporal constraints. In this paper, we propose an efficie...
Zhao Xing, Yixin Chen, Weixiong Zhang