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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
14 years 1 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
IPPS
2010
IEEE
13 years 5 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
IPPS
2000
IEEE
13 years 12 months ago
Reduction Optimization in Heterogeneous Cluster Environments
Network of workstation (NOW) is a cost-effective alternative to massively parallel supercomputers. As commercially available off-the-shelf processors become cheaper and faster, ...
Pangfeng Liu, Da-Wei Wang
BMEI
2008
IEEE
14 years 2 months ago
A New Approach for Tree Alignment Based on Local Re-Optimization
Multiple sequence alignment is the most fundamental task in bioinformatics and computational biology. In this paper, we present a new algorithm to conduct multiple sequences align...
Feng Yue, Jijun Tang
PPOPP
2010
ACM
14 years 4 months ago
Lazy binary-splitting: a run-time adaptive work-stealing scheduler
We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing...
Alexandros Tzannes, George C. Caragea, Rajeev Baru...