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DATE
2007
IEEE
133views Hardware» more  DATE 2007»
14 years 1 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...
ICPPW
2009
IEEE
14 years 2 months ago
CkDirect: Unsynchronized One-Sided Communication in a Message-Driven Paradigm
A significant fraction of parallel scientific codes are iterative with barriers between iterations or even between phases of the same iteration. The sender of a message is assur...
Eric J. Bohm, Sayantan Chakravorty, Pritish Jetley...
PDP
2008
IEEE
14 years 1 months ago
Just-In-Time Scheduling for Loop-based Speculative Parallelization
Scheduling for speculative parallelization is a problem that remained unsolved despite its importance. Simple methods such as Fixed-Size Chunking (FSC) need several ‘dry-runs’...
Diego R. Llanos Ferraris, David Orden, Belé...
CGO
2008
IEEE
14 years 2 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
DAC
1996
ACM
13 years 11 months ago
A Register File and Scheduling Model for Application Specific Processor Synthesis
In this paper, we outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive ite...
Ehat Ercanli, Christos A. Papachristou