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133
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ARITH
1999
IEEE
15 years 7 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
114
Voted
MICRO
1999
IEEE
108views Hardware» more  MICRO 1999»
15 years 6 months ago
Exploiting ILP in Page-based Intelligent Memory
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
Mark Oskin, Justin Hensley, Diana Keen, Frederic T...
138
Voted
SIGGRAPH
1998
ACM
15 years 6 months ago
A Shading Language on Graphics Hardware: The Pixelflow Shading System
Over the years, there have been two main branches of computer graphics image-synthesis research; one focused on interactivity, the other on image quality. Procedural shading is a ...
Marc Olano, Anselmo Lastra
138
Voted
ICDE
2010
IEEE
290views Database» more  ICDE 2010»
15 years 6 months ago
The Model-Summary Problem and a Solution for Trees
Modern science is collecting massive amounts of data from sensors, instruments, and through computer simulation. It is widely believed that analysis of this data will hold the key ...
Biswanath Panda, Mirek Riedewald, Daniel Fink
112
Voted
SIGGRAPH
1994
ACM
15 years 6 months ago
FBRAM: a new form of memory optimized for 3D graphics
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
Michael F. Deering, Stephen A. Schlapp, Michael G....