We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
Sybille Hellebrand, Christian G. Zoellin, Hans-Joa...
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
Statistical methods to model check stochastic systems have been, thus far, developed only for a sublogic of continuous stochastic logic (CSL) that does not have steady state operat...