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» Parallel Memory Architecture for Arbitrary Stride Accesses
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SIPS
2006
IEEE
14 years 1 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
HPCA
2007
IEEE
14 years 8 months ago
MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging
Memory bugs are a broad class of bugs that is becoming increasingly common with increasing software complexity, and many of these bugs are also security vulnerabilities. Unfortuna...
Guru Venkataramani, Brandyn Roemer, Yan Solihin, M...
IPPS
2002
IEEE
14 years 14 days ago
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
Brian R. Gaeke, Parry Husbands, Xiaoye S. Li, Leon...
ISPASS
2007
IEEE
14 years 1 months ago
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications
—Although SIMD extensions are a cost effective way to exploit the data level parallelism present in most media applications, we will show that they had have a very limited memory...
Mauricio Alvarez, Esther Salamí, Alex Ram&i...
FPL
1999
Springer
80views Hardware» more  FPL 1999»
13 years 11 months ago
An Internet Based Development Framework for Reconfigurable Computing
The paper presents a development framework for the Xputer prototype Map-oriented Machine with Parallel Data Access (MoM-PDA). The MoM-PDA operates as a reconfigurable accelerator t...
Reiner W. Hartenstein, Michael Herz, Ulrich Nageld...