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» Parallel Memory Architecture for Arbitrary Stride Accesses
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SPAA
2000
ACM
13 years 12 months ago
Algorithmic foundations for a parallel vector access memory system
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with str...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
IPPS
2007
IEEE
14 years 1 months ago
Improving Scalability of OpenMP Applications on Multi-core Systems Using Large Page Support
Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the...
Ranjit Noronha, Dhabaleswar K. Panda
SAMOS
2007
Springer
14 years 1 months ago
High-Bandwidth Address Generation Unit
In this paper we describe an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed address ...
Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjie...
ICS
2000
Tsinghua U.
13 years 11 months ago
Hardware-only stream prefetching and dynamic access ordering
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
Chengqiang Zhang, Sally A. McKee
CODES
2005
IEEE
14 years 1 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...