309 search results - page 43 / 62 » Parallel Memory Architecture for Arbitrary Stride Accesses |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
SC
1995
ACM
13 years 11 months ago
1995
ACM
: Data distribution is one of the key aspects that a parallelizing compiler for a distributed memory architecture should consider, in order to get efficiency from the system. The ...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transaction's readand writ...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...