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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
14 years 1 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
ERSA
2007
142views Hardware» more  ERSA 2007»
13 years 11 months ago
An FPGA Implementation of Reciprocal Sums for SPME
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...
Sam Lee, Paul Chow
HPDC
1995
IEEE
14 years 1 months ago
Loop Scheduling for Heterogeneity
In this paper, we study the problem of scheduling parallel loops at compile-time for a heterogeneous network of machines. We consider heterogeneity in three aspects of parallel pr...
Michal Cierniak, Wei Li, Mohammed Javeed Zaki
IPPS
1999
IEEE
14 years 1 months ago
Implementing a Non-Strict Functional Programming Language on a Threaded Architecture
Abstract. The combination of a language with ne-grain implicit parallelism and a data ow evaluation scheme is suitable for high-level programming on massively parallel architectur...
Shigeru Kusakabe, Kentaro Inenaga, Makoto Amamiya,...
DAC
2007
ACM
14 years 10 months ago
Implicitly Parallel Programming Models for Thousand-Core Microprocessors
This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly paralle...
Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H....