127 search results - page 4 / 26 » Parallel Performance Prediction for Multigrid Codes on Distr... |
PPOPP
2010
ACM
14 years 5 months ago
2010
ACM
Transactional memory promises to make parallel programming easier than with fine-grained locking, while performing just as well. This performance claim is not always borne out bec...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
HPCA
2001
IEEE
14 years 9 months ago
2001
IEEE
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
EUROPAR
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. Accurately modeling and predicting performance for largescale applications becomes increasingly difficult as system complexity scales dramatically. Analytic predictive mo...