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» Parallel Processing Architectures for Reconfigurable Systems
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2005
IEEE
14 years 3 months ago
Load Balancing using Grid-based Peer-to-Peer Parallel I/O
In the area of Grid computing, there is a growing need to process large amounts of data. To support this trend, we need to develop efficient parallel storage systems that can prov...
Yijian Wang, David R. Kaeli
LCPC
2001
Springer
14 years 2 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann
ANCS
2010
ACM
13 years 8 months ago
The case for hardware transactional memory in software packet processing
Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and acceler...
Martin Labrecque, J. Gregory Steffan
ET
2002
115views more  ET 2002»
13 years 10 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
HPCC
2009
Springer
14 years 2 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig