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» Parallel Programming with Transactional Memory
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ASPLOS
2011
ACM
13 years 2 days ago
On-the-fly elimination of dynamic irregularities for GPU computing
The power-efficient massively parallel Graphics Processing Units (GPUs) have become increasingly influential for scientific computing over the past few years. However, their ef...
Eddy Z. Zhang, Yunlian Jiang, Ziyu Guo, Kai Tian, ...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
14 years 3 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi
DAC
2007
ACM
14 years 9 months ago
Hardware Support for Secure Processing in Embedded Systems
The inherent limitations of embedded systems make them particularly vulnerable to attacks. We have developed a hardware monitor that operates in parallel to the embedded processor...
Shufu Mao, Tilman Wolf
DATE
2008
IEEE
138views Hardware» more  DATE 2008»
14 years 2 months ago
Functional Self-Testing for Bus-Based Symmetric Multiprocessors
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
Andreas Apostolakis, Dimitris Gizopoulos, Mihalis ...
BIBE
2007
IEEE
150views Bioinformatics» more  BIBE 2007»
14 years 2 months ago
Differential Scoring for Systolic Sequence Alignment
Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course- and fine-grain parallelization. A ...
Antonio E. de la Serna