1075 search results - page 204 / 215 » Parallel Programming with Transactional Memory |
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
IEEEPACT
2009
IEEE
14 years 3 months ago
2009
IEEE
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
ICMCS
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
CTRSA
2007
Springer
14 years 2 months ago
2007
Springer
This paper announces a new software side-channel attack — enabled by the branch prediction capability common to all modern highperformance CPUs. The penalty paid (extra clock cyc...