185 search results - page 23 / 37 » Parallel Sorting with Limited Bandwidth |
ICMCS
2008
IEEE
14 years 1 months ago
2008
IEEE
This research establishes the feasibility of using a network centric technology, Jini, to provide a grid framework on which to perform parallel video encoding. A solution was impl...
CVPR
2011
IEEE
13 years 2 months ago
2011
IEEE
We present the design and implementation of new inexact Newton type Bundle Adjustment algorithms that exploit hardware parallelism for efficiently solving large scale 3D scene re...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
IISWC
2009
IEEE
14 years 2 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
On a distributed memory machine, hand-coded message passing leads to the most efficient execution, but it is difficult to use. Parallelizing compilers can approach the performance...