462 search results - page 16 / 93 » Parallel algorithm for hardware implementation of inverse ha... |
ISLPED
1996
ACM
13 years 11 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
ESAS
2004
Springer
14 years 3 days ago
2004
Springer
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
ARC
2009
Springer
14 years 1 months ago
2009
Springer
Abstract. This paper presents implementation results of a reconfigurable elliptic curve processor defined over prime fields GF(p). We use this processor to compare a new algorit...
ARC
2012
Springer
12 years 2 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...