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IPPS
2008
IEEE
14 years 1 months ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 11 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
WCE
2007
13 years 8 months ago
High-Performance Multigrid Solvers in Reconfigurable Hardware
—Partial Differential Equations (PDEs) play an essential role in modeling real world problems. The broad field of modeling such systems has drawn the researchers’ attention for...
Safaa J. Kasbah, Issam W. Damaj
ICASSP
2009
IEEE
14 years 2 months ago
Bandwidth adaptive hardware architecture of K-Means clustering for intelligent video processing
K-Means is a clustering algorithm that is widely applied in many elds, including pattern classi cation and multimedia analysis. Due to real-time requirements and computational-cos...
Tse-Wei Chen, Shao-Yi Chien
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III