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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
13 years 10 months ago
Use of embedded scheduling to compile VHDL for effective parallel simulation
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
John Willis, Zhiyuan Li, Tsang-Puu Lin
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
13 years 11 months ago
Parallel and Distributed VHDL Simulation
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Dragos Lungeanu, C.-J. Richard Shi
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 11 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
15
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EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 11 months ago
Distributed simulation for structural VHDL netlists
: This article describes the current state of the project to develop distributed simulation. The reader will have
David B. Bernstein, Werner van Almsick, Wilfried D...