Sciweavers

1995 search results - page 318 / 399
» Parallel and Distributed VHDL Simulation
Sort
View
SPAA
1998
ACM
15 years 6 months ago
Lamport Clocks: Verifying a Directory Cache-Coherence Protocol
Modern shared-memory multiprocessors use complex memory system implementations that include a variety of non-trivial and interacting optimizations. More time is spent in verifying...
Manoj Plakal, Daniel J. Sorin, Anne Condon, Mark D...
102
Voted
IEEEPACT
2008
IEEE
15 years 8 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
PODC
2003
ACM
15 years 7 months ago
Scaling properties of the Internet graph
As the Internet grows in size, it becomes crucial to understand how the speeds of links in the network must improve in order to sustain the pressure of new end-nodes being added e...
Aditya Akella, Shuchi Chawla, Arvind Kannan, Srini...
TC
2010
14 years 9 months ago
Scheduling Concurrent Bag-of-Tasks Applications on Heterogeneous Platforms
Abstract-- Scheduling problems are already difficult on traditional parallel machines, and they become extremely challenging on heterogeneous clusters. In this paper we deal with t...
Anne Benoit, Loris Marchal, Jean-Francois Pineau, ...
HPCA
2008
IEEE
16 years 2 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...