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» Parallel fault backtracing for calculation of fault coverage
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IEEEPACT
2008
IEEE
14 years 3 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
DSD
2007
IEEE
140views Hardware» more  DSD 2007»
14 years 3 months ago
Pseudo-Random Pattern Generator Design for Column-Matching BIST
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
Petr Fiser
DFT
2004
IEEE
101views VLSI» more  DFT 2004»
14 years 10 days ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
IPPS
2005
IEEE
14 years 2 months ago
On Constructing k-Connected k-Dominating Set in Wireless Networks
An important problem in wireless networks, such as wireless ad hoc and sensor networks, is to select a few nodes to form a virtual backbone that supports routing and other tasks s...
Fei Dai, Jie Wu
CCGRID
2010
IEEE
13 years 9 months ago
Region-Based Prefetch Techniques for Software Distributed Shared Memory Systems
Although shared memory programming models show good programmability compared to message passing programming models, their implementation by page-based software distributed shared m...
Jie Cai, Peter E. Strazdins, Alistair P. Rendell