193 search results - page 12 / 39 » Parallel performance evaluation through critical path analys... |
INFOCOM
2005
IEEE
14 years 29 days ago
2005
IEEE
—The communication model typically assumed in wireless ad-hoc networks is based on a traditional “pipelined relay” (PR) strategy. In PR, an end-to-end flow has multiple outs...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
3DIC
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Flash memory based solid state drives (SSDs) have shown a great potential to change storage infrastructure fundamentally through their high performance and low power. Most recent ...