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» Parallel processing flow models on desktop hardware
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TCSV
2002
119views more  TCSV 2002»
13 years 8 months ago
VLSI architecture design of MPEG-4 shape coding
This paper presents an efficient VLSI architecture design of MPEG-4 shape coding, which is the key technology for supporting the content-based functionality of the MPEG-4 Video sta...
Hao-Chieh Chang, Yung-Chi Chang, Yi-Chu Wang, Wei-...
IPPS
2007
IEEE
14 years 2 months ago
A Performance Prediction Framework for Grid-Based Data Mining Applications
For a grid middleware to perform resource allocation, prediction models are needed, which can determine how long an application will take for completion on a particular platform o...
Leonid Glimcher, Gagan Agrawal
CF
2006
ACM
14 years 2 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
ISLPED
2005
ACM
93views Hardware» more  ISLPED 2005»
14 years 2 months ago
Power-aware code scheduling for clusters of active disks
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
Seung Woo Son, Guangyu Chen, Mahmut T. Kandemir
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 6 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt