Sciweavers

360 search results - page 70 / 72
» Parallel processing flow models on desktop hardware
Sort
View
IEEEPACT
2008
IEEE
14 years 1 months ago
A tuning framework for software-managed memory hierarchies
Achieving good performance on a modern machine with a multi-level memory hierarchy, and in particular on a machine with software-managed memories, requires precise tuning of progr...
Manman Ren, Ji Young Park, Mike Houston, Alex Aike...
FPL
2004
Springer
125views Hardware» more  FPL 2004»
14 years 25 days ago
SoftSONIC: A Customisable Modular Platform for Video Applications
This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application developraising the level of abstraction and facilitating design reus...
Tero Rissa, Peter Y. K. Cheung, Wayne Luk
CIDR
2003
123views Algorithms» more  CIDR 2003»
13 years 8 months ago
A Case for Staged Database Systems
Traditional database system architectures face a rapidly evolving operating environment, where millions of users store and access terabytes of data. In order to cope with increasi...
Stavros Harizopoulos, Anastassia Ailamaki
LCTRTS
2009
Springer
14 years 2 months ago
Synergistic execution of stream programs on multicores with accelerators
The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. The StreamIt graphs describe task, da...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
HPCA
2005
IEEE
14 years 7 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...