104 search results - page 19 / 21 » Parallel processor scheduling with delay constraints |
CATA
2003
13 years 11 months ago
2003
This paper presents a basic framework for applying static task scheduling techniques to arbitrarily-structured task systems whose targeted execution environment is comprised of fi...
HPCA
2005
IEEE
14 years 10 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
ICS
2009
Tsinghua U.
14 years 4 months ago
2009
Tsinghua U.
Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time...
IPPS
2000
IEEE
14 years 2 months ago
2000
IEEE
Conventional concurrency control protocols are inapplicable in mobile computing environments due to a number of constraints of wireless communications. In this paper, we design a p...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Recently, under a fixed power budget, asymmetric multiprocessors (AMP) have been proposed to improve the performance of multi-threaded applications compared to symmetric multiproc...