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» Parallel programmable video co-processor design
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JRTIP
2008
118views more  JRTIP 2008»
13 years 7 months ago
Custom parallel caching schemes for hardware-accelerated image compression
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...
GI
2004
Springer
14 years 1 months ago
Distributed Job Scheduling in a Peer-to-Peer Video Recording System
: Since the advent of Gnutella, Peer-to-Peer (P2P) protocols have matured towards a fundamental design element for large-scale, self-organising distributed systems. Many research e...
Curt Cramer, Kendy Kutzner, Thomas Fuhrmann
VLSISP
2008
123views more  VLSISP 2008»
13 years 7 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
SASP
2008
IEEE
153views Hardware» more  SASP 2008»
14 years 2 months ago
TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing
Ray tracing is a technique used for generating highly realistic computer graphics images. In this paper, we explore the design of a simple but extremely parallel, multi-threaded, ...
Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik...
CASES
2008
ACM
13 years 9 months ago
SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip
fficient Programming Abstractions for Heterogeneous Multicore Systems on Chip Alastair D. Reid Krisztian Flautner Edmund Grimley-Evans ARM Ltd Yuan Lin University of Michigan The ...
Alastair D. Reid, Krisztián Flautner, Edmun...