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» Parallel signal processing with S-Net
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FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 1 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
IPPS
2009
IEEE
14 years 2 months ago
DMTCP: Transparent checkpointing for cluster computations and the desktop
DMTCP (Distributed MultiThreaded CheckPointing) is a transparent user-level checkpointing package for distributed applications. Checkpointing and restart is demonstrated for a wid...
Jason Ansel, Kapil Arya, Gene Cooperman
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
14 years 23 days ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
SPAA
2005
ACM
14 years 29 days ago
Value-maximizing deadline scheduling and its application to animation rendering
We describe a new class of utility-maximization scheduling problem with precedence constraints, the disconnected staged scheduling problem (DSSP). DSSP is a nonpreemptive multipro...
Eric Anderson, Dirk Beyer 0002, Kamalika Chaudhuri...
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
14 years 1 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...