770 search results - page 110 / 154 » Parallel simulation of chip-multiprocessor architectures |
IJCNN
2007
IEEE
14 years 5 months ago
2007
IEEE
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
: In this paper, we have proposed a time efficient, energy saving and robust broadcast/multicast protocol for reconfigurable cluster-based sensor network. In our broadcast protocol...
ISCAS
2007
IEEE
14 years 5 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
SAC
2004
ACM
14 years 4 months ago
2004
ACM
An import issue for numerical weather prediction modes (NWP) is the time it takes to produce a valid forecast. One factor, which greatly influences this simulation time is the si...
SC
2004
ACM
14 years 4 months ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...