770 search results - page 114 / 154 » Parallel simulation of chip-multiprocessor architectures |
ISSS
1998
IEEE
14 years 23 days ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
ISCA
2011
IEEE
13 years 6 days ago
2011
IEEE
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
JSSPP
2004
Springer
14 years 1 months ago
2004
Springer
Using a single traditional gang scheduling algorithm cannot provide the best performance for all workloads and parallel architectures. A solution for this problem is the use of...
IPPS
2000
IEEE
14 years 27 days ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
PODC
1994
ACM
14 years 18 days ago
1994
ACM
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...