TLSync: support for multiple fast barriers using on-chip transmission lines

As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament barrier, a larger number of cores results in a longer latency for each round and a larger number of rounds. Hardware barrier implementations require significant dedicated wiring, e.g., using a reduction (arrival) tree and a notification (release) tree, and multiple instances of this wiring are needed to support multiple barriers (e.g., when concurrently executing multiple parallel applications). This paper presents TLSync, a novel hardware barrier implementation that uses the high-frequency part of the spectrum in a transmission-line broadcast network, thus leaving the transmission line network free for non-modulated (baseband) data transmission. In contrast to other implementations of hardware barriers, TLSync allows multiple thread groups to each have its own barrier. This is accomplished by allocating di�...

• Type: Journal
• Year: 2011
• Where: ISCA
• Authors: Jungju Oh, Milos Prvulovic, Alenka G. Zajic
• Keywords: Architectural Simulations, Barrier Synchronization, Hardware, ISCA 2011, Radio Frequency Spectrum