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» Parallel simulation of chip-multiprocessor architectures
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DATE
2005
IEEE
108views Hardware» more  DATE 2005»
14 years 2 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
EUROPAR
2003
Springer
14 years 1 months ago
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer
Hardware performance monitoring is the basis of modern performance analysis tools for application optimization. We are interested in providing such performance analysis tools for t...
Pedro Mindlin, José R. Brunheroto, Luiz De ...
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
14 years 1 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
ISCC
2002
IEEE
144views Communications» more  ISCC 2002»
14 years 1 months ago
A hierarchical distributed protocol for MPLS path creation
Network service provisioning involves the control of network resources through signaling, routing and management protocols that achieve Quality of Service and Traffic Engineering ...
Mohamed El-Darieby, Dorina C. Petriu, Jerry Rolia
EUROMICRO
1999
IEEE
14 years 23 days ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen