770 search results - page 149 / 154 » Parallel simulation of chip-multiprocessor architectures |
ICS
2007
Tsinghua U.
14 years 2 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
CF
2010
ACM
14 years 1 months ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
ICS
2009
Tsinghua U.
14 years 1 months ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
SIAMCOMP
2000
13 years 8 months ago
2000
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...