770 search results - page 14 / 154 » Parallel simulation of chip-multiprocessor architectures |
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
TPDS
2008
13 years 7 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
MICRO
2010
IEEE
13 years 6 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
CAL
2008
13 years 8 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...