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» Parallel simulation of chip-multiprocessor architectures
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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 6 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
EUROPAR
2004
Springer
14 years 1 months ago
Large-Scale Deployment in P2P Experiments Using the JXTA Distributed Framework
The interesting properties of P2P systems (high availability despite peer volatility, support for heterogeneous architectures, high scalability, etc.) make them attractive for dist...
Gabriel Antoniu, Luc Bougé, Mathieu Jan, S&...
DAC
2006
ACM
14 years 9 months ago
Stochastic variational analysis of large power grids considering intra-die correlations
For statistical timing and power analysis that are very important problems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctua...
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhar...
CHI
2009
ACM
14 years 9 months ago
PenLight: combining a mobile projector and a digital pen for dynamic visual overlay
Digital pen systems, originally designed to digitize annotations made on physical paper, are evolving to permit a wider variety of applications. Although the type and quality of p...
Hyunyoung Song, Tovi Grossman, George W. Fitzmauri...
HPCA
2009
IEEE
14 years 9 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth