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» Parallel simulation of chip-multiprocessor architectures
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GRID
2005
Springer
15 years 9 months ago
SERVOGrid complexity computational environments (CCE) integrated performance analysis
In this paper we describe the architecture and initial performance analysis results of the SERVOGrid Complexity Computational Environments (CCE). The CCE architecture is based on ...
Galip Aydin, Mehmet S. Aktas, Geoffrey Fox, Harsha...
134
Voted
IPPS
2003
IEEE
15 years 8 months ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
130
Voted
CLUSTER
2007
IEEE
15 years 3 months ago
The computer as software component: A mechanism for developing and testing resource management software
— In this paper, we present an architecture that encapsulates system hardware inside a software component used for job execution and status monitoring. The development of this in...
Narayan Desai, Theron Voran, Ewing L. Lusk, Andrew...
137
Voted
IPPS
2010
IEEE
15 years 1 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...
127
Voted
IPPS
1998
IEEE
15 years 7 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...