1761 search results - page 22 / 353 » Parallel timing simulation on a distributed memory multiproc... |
126
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HPCA
2000
IEEE
15 years 7 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
139
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IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
122
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HPCA
1995
IEEE
15 years 6 months ago
1995
IEEE
In this paper we consider several hardware implementations of the general-purpose atomic primitives fetch and Φ, compare and swap, load linked, and store conditionalon large-scal...
139
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HPDC
1998
IEEE
15 years 7 months ago
1998
IEEE
This paper introduces Strings, a high performance distributed shared memory system designed for clusters of symmetrical multiprocessors (SMPs). The distinguishing feature of this ...
119
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EUROPAR
2004
Springer
15 years 8 months ago
2004
Springer
Abstract. Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the caus...