1761 search results - page 274 / 353 » Parallel timing simulation on a distributed memory multiproc... |
HPCA
2001
IEEE
14 years 9 months ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
ICS
2010
Tsinghua U.
14 years 1 months ago
2010
Tsinghua U.
We explore the intersection between an emerging class of architectures and a prominent workload: GPGPUs (General-Purpose Graphics Processing Units) and regular expression matching...
ISCAPDCS
2003
13 years 10 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
GRID
2007
Springer
13 years 9 months ago
2007
Springer
Combining Grid and P2P technologies can be exploited to provide high-level data sharing in large-scale distributed environments. However, this combination must deal with two hard p...
ICDCSW
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper we investigate the performance of IEEE 802.11 ad hoc networks by means of an experimental study. Measurements on IEEE 802.11 ad hoc networks confirm previous sim...