1761 search results - page 6 / 353 » Parallel timing simulation on a distributed memory multiproc... |
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
HPCC
2005
Springer
14 years 1 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
—Lattice Boltzmann Methods (LBM) are used for the computational simulation of Newtonian fluid dynamics. LBM-based simulations are readily parallelizable; they have been implemen...
JSA
2007
13 years 7 months ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and s...