Sciweavers

1016 search results - page 146 / 204
» Parallelism Constraints
Sort
View
151
Voted
HPCA
2012
IEEE
13 years 10 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
112
Voted
CF
2010
ACM
15 years 7 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
ECAI
2004
Springer
15 years 8 months ago
IPSS: A Hybrid Reasoner for Planning and Scheduling
In this paper we describe IPSS (Integrated Planning and Scheduling System), a domain independent solver that integrates an AI heuristic planner, that synthesizes courses of actions...
María Dolores Rodríguez-Moreno, Ange...
126
Voted
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
15 years 11 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
137
Voted
ALGORITHMICA
2002
120views more  ALGORITHMICA 2002»
15 years 2 months ago
An Experimental Study of Algorithms for Weighted Completion Time Scheduling
We consider the total weighted completion time scheduling problem for parallel identical machines and precedence constraints, P jprecj PwiCi. This important and broad class of pro...
Ivan D. Baev, Waleed Meleis, Alexandre E. Eichenbe...