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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 2 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
FMCO
2003
Springer
121views Formal Methods» more  FMCO 2003»
14 years 2 months ago
TulaFale: A Security Tool for Web Services
Web services security specifications are typically expressed as a mixture of XML schemas, example messages, and narrative explanations. We propose a new specification language fo...
Karthikeyan Bhargavan, Cédric Fournet, Andr...
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 2 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
CF
2010
ACM
14 years 2 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
14 years 1 months ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
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