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» Parallelism through Digital Circuit Design
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MSO
2003
13 years 9 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
TCAD
2008
81views more  TCAD 2008»
13 years 7 months ago
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
Stephen Plaza, Igor L. Markov, Valeria Bertacco
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 1 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ICDE
2010
IEEE
248views Database» more  ICDE 2010»
14 years 7 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...
IJVR
2007
202views more  IJVR 2007»
13 years 7 months ago
Full Solid Angle Panoramic Viewing by Depth Image Warping on Field Programmable Gate Array
—To construct 3D virtual scenes from two-dimensional images with depth information, image warping techniques could be used. In this paper, a novel approach of cylindrical depth i...
Xiaoying Li, Baoquan Liu, Enhua Wu