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HPCC
2009
Springer
14 years 23 hour ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
IPPS
1997
IEEE
13 years 11 months ago
Cyclic Networks: A Family of Versatile Fixed-Degree Interconnection Architectures
In this paper, we propose a new family of interconnection networks, called cyclic networks (CNs), in which an intercluster connection is defined on a set of nodes whose addresses...
Chi-Hsiang Yeh, Behrooz Parhami
MABS
2004
Springer
14 years 23 days ago
Smooth Scaling Ahead: Progressive MAS Simulation from Single PCs to Grids
The emerging ”Computational Grid” infrastructure poses many new opportunities for the developing science of large scale multiagent simulation. The ability to migrate agent expe...
Les Gasser, Kelvin Kakugawa, Brant Chee, Marc Este...
MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
13 years 11 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
VLSISP
2010
119views more  VLSISP 2010»
13 years 2 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton